1. Field of the Invention
The present invention relates to a content addressable memory (referred to as a CAM hereinafter) device having CAM cells, and in particular, to a CAM device having a match line equalizer circuit.
2. Description of the Related Art
Recently, a CAM device having CAM cells or ternary CAM (referred to as a TCAM hereinafter) cells (these CAM cells are generally referred to as CAM cells hereinafter) has been employed in a retrieval unit for network address paths or the like. Each CAM cell is constructed by including one storage cell for storing binary storage data of “0” and “1”, a search line for searching two search data of “0” and “1”, a match line, and a comparator circuit. In this case, the comparator circuit compares the search data from the search line with the storage data of the storage cell, and outputs a signal indicating a result of the comparison to the match line. In addition, each TCAM cell is constructed by including two storage cells for storing three-value storage data of “0”, “1”, and “X (Don't care; indefinite value), a pair of search lines for searching two search data of “0” and “1”, a match line, and a comparator circuit. The comparator circuit compares the search data from the pair of search lines with the storage data of the storage cells, and outputs a signal indicating a result of the comparison to the match line. In this case, the match line is precharged to a high level in advance, and discharged in response to a signal outputted from the comparator circuit indicating that the search data is unmatched with the storage data. This search operation is a parallel operation that can be simultaneously executed on all entries of search targets in a CAM array constituted by a plurality of CAM cells or TCAM cells. Therefore, it is possible to perform the data search at high speed in the CAM device.
However, the following problems have become obvious for the CAM device constructed by including CAM cells. For an interval of the above-stated search operation, relatively large peak current flows when charging and discharging the match line and charging and discharge of the search line. In addition, an increase in a capacity of the CAM array leads to an increased peak current and relatively large voltage drop, and the increased peak current causes an electromagnetic interference and a power-supply noise. Further, the increase in the capacity of the CAM array also leads to an increased total current consumption of the CAM device. As measures against these problems, it is necessary to thicken the power source wirings in order to reduce the impedances of the power source and ground lines, increase the number of the power source pads, reduce the impedance of the package, and intensify the power source of the circuit board on which a CAM LSI is mounted. It is also necessary to take such measures as arrangement of a radiation fin in order to handle an increased amount of heat following the increased current. However, each of these measures disadvantageously leads to increased costs of an LSI for the CAM, and operation margin such as the operation of the power source at the lower limit and the operating frequency deteriorates. These problems are major problem making it difficult to increase the capacity of the CAM array.
In a CAM device according to a prior art disclosed in the Japanese patent laid-open publication No. JP-2006-309917-A, a ternary memory, a match comparator circuit, and a search line activation control circuit are provided for each of the divided sub arrays. First of all, an arbitrary sub array is selected by match comparison of a second search request for arbitrarily designating a plurality of divided sub arrays with a value stored in the ternary memory. The match comparator circuit provided in the selected sub array transmits a series data obtained by a first search request to the search line activation control circuit. Therefore, it is possible to realize low power consumption by adding a simple hardware.
The Japanese patent laid-open publication No. JP-2004-295986-A discloses a semiconductor memory device according to a prior art constructed by including (a) a CAM cell block to which storage data expressing a combination of digital values stored in four memory cells, respectively, by a two-bit digital value, (b) a search line to which a digital value is set to that is to be match-compared with the digital value stored in each of the memory cells, (c) a search data setting unit for setting a one-bit digital value to the search line connected to each of the memory cells and setting search data expressing a combination of four-bit digital values by a two-bit digital value, (d) a transistor determining whether the storage data is matched or unmatched with the search data, and (e) a match line for outputting a result indicating this determination. Since the frequency of activation of the search line is reduced in the search operation, the power consumption can be reduced.
The Japanese patent laid-open publication No. JP-2002-358791-A discloses a CAM device according to a prior art configured as follows. The CAM device includes (a) a first match line that is a first part obtained by dividing one match line corresponding to one entry data into two parts and whose electric potential changes from a first electric potential to a second electric potential in the case of an unmatched condition, (b) a second match line that is a second part obtained by dividing the above match line and whose electric potential changes from the second electric potential to the first electric potential in the case of the unmatched condition, (c) a first precharge circuit for precharging the first match line to the first electric potential, (d) a second precharge circuit for precharging the second match line to the second electric potential, and (e) a short circuit short-circuiting the first and second match lines to each other before the precharge operations by the first and second precharge circuit when both of the first and second match lines are in the unmatched condition. By precharging or discharging each of the match lines after the short-circuiting, the power consumption can be reduced.
However, the CAM devices or semiconductor memory devices according to the prior art have such a problem that the power consumption and the peak current cannot be further reduced.